Title :
Limiting factors for SOI VLSI high-level hardness: modeling and improving
Author :
Leray, J.L. ; Dupont-Nivet, E. ; Péré, J.F. ; Musseau, O. ; Lalande, P. ; Umbert, A.
Author_Institution :
CEA-DAM, Bruyeres-Le-Chatel, France
Abstract :
Summary form only given. Some radiation hardness limiting mechanisms specific to SOI, at the elementary level and at the large-scale circuit level, are discussed. It is shown that LSI hardness at the 10 Megarad (Si) level is possible, and what kind of problems can be experienced beyond 100 Megarad (Si)
Keywords :
VLSI; elemental semiconductors; radiation hardening (electronics); semiconductor device models; semiconductor technology; semiconductor-insulator boundaries; silicon; 107 to 108 rad; SOI; VLSI; elementary level; high-level hardness; large-scale circuit level; limiting factors; modeling; radiation hardness limiting mechanisms; semiconductors; Board of Directors; Circuits; Large scale integration; Large-scale systems; Manufacturing; Propagation delay; Silicon; Substrates; Testing; Very large scale integration;
Conference_Titel :
SOS/SOI Technology Conference, 1989., 1989 IEEE
Conference_Location :
Stateline, NV
DOI :
10.1109/SOI.1989.69793
