Title :
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC
Author :
Zhu, Yan ; Chan, Chi-Hang ; Sin, Sai-Weng ; U, Seng-Pan ; Martins, R.P.
Author_Institution :
State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China
Abstract :
A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; CMOS process; energy 34 fJ; full-speed SAR; mean SNDR; offset calibrations; operational amplifier; partial-interleaving pipelined SAR ADC; pipelined residue amplification; power 8.2 mW; power dissipation; second-stage SAR ADC; shared opamp; size 65 nm; voltage 1.2 V; word length 10 bit; CMOS integrated circuits; Calibration; Capacitance; Error correction; Semiconductor device measurement; Switches; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243804
