Title :
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS
Author :
Tai, Hung-Yen ; Chen, Hung-Wei ; Chen, Hsin-Shu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.
Keywords :
CMOS logic circuits; analogue-digital conversion; digital-analogue conversion; microcontrollers; CMOS technology; DAC common mode level shift; FOM; Nyquist rate; SNDR; arbitrary weight capacitor array; bit rate 100 kbit/s; charge pump; differential control logic; leakage reduction sample; low-voltage energy-efficient SAR ADC; power 170 nW; size 90 nm; voltage 0.35 V; Capacitors; Charge pumps; Clocks; Energy efficiency; Low voltage; MOS devices; Switches; Low voltage; SAR ADC; low power;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243805
