Title :
A 22nm dynamically adaptive clock distribution for voltage droop tolerance
Author :
Bowman, Keith A. ; Tokunaga, Carlos ; Karnik, Tanay ; De, Vivek K. ; Tschanz, Jim W.
Author_Institution :
Circuit Res. Lab., Intel, Hillsboro, OR, USA
Abstract :
A 22nm all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (VCC) droops on microprocessor performance and energy efficiency. Silicon measurements demonstrate simultaneous throughput gains and energy reductions ranging from 14% and 3% at 1.0V to 31% and 15% at 0.6V, respectively, for a 10% VCC droop.
Keywords :
clock distribution networks; microprocessor chips; all-digital dynamically adaptive clock distribution; energy efficiency; energy reductions; high-frequency supply voltage droop; microprocessor performance; silicon measurements; simultaneous throughput gains; size 22 mm; voltage 0.6 V; voltage droop tolerance; Clocks; Delay; Pipelines; Time factors; Time frequency analysis;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243806
