DocumentCode :
2661407
Title :
Voltage droop reduction using throttling controlled by timing margin feedback
Author :
Floyd, Michael S. ; Drake, Alan J. ; Berry, Robert W. ; Chase, Harold ; Willaman, Richard ; Pena, Jarom
Author_Institution :
Syst. & Technol. Group, IBM, Austin, TX, USA
fYear :
2012
fDate :
13-15 June 2012
Firstpage :
96
Lastpage :
97
Abstract :
An active processor throttling control loop using critical path timing measurements is enabled in the shipping POWER7™ based P775 supercomputer to prevent voltage droop induced failures. As a result, worst-case workload-induced voltage droop events are reduced by more than 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates, and improved power efficiency.
Keywords :
VLSI; failure analysis; integrated circuit reliability; mainframes; power integrated circuits; VLSI; active processor throttling control loop; critical path timing measurements; power efficiency; shipping POWER7 based P775 supercomputer; timing margin feedback; voltage droop induced failures; voltage droop reduction; worst-case workload-induced voltage droop events; Instruction sets; Process control; Supercomputers; Timing; Very large scale integration; Voltage control; Voltage measurement; VLSI; critical path; reliability; voltage droop;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
Type :
conf
DOI :
10.1109/VLSIC.2012.6243807
Filename :
6243807
Link To Document :
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