A novel low power hybrid flipflop using sleepy stack inverter pair

This paper presents a low power hybrid flip flop using sleepy stack inverter pair for retaining the logic level till the end of evaluation and pre-charge phase of the flip flop. The sleepy stack inverter pairs are efficient in leakage power reduction and overall power dissipation as the technology scales down to 90nm and below. The performance of the proposed flip flop was compared with the conventional dual dynamic node pulsed hybrid flip flop (DDFF) which uses conventional static CMOS inverter pairs in cadence virtuoso 90nm tool. It shows 20% reduction in total power consumed with 89% reduction in leakage power at its output node. T flip flop, SR flip flop and JK flip flop were designed using this proposed D flip flop and its performance was compared with flip flops designed using DDFF. As the proposed flip flops have improved performance in terms of leakage power, total power and power delay product at high speed, it can be widely used in high performance applications.