Title :
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs
Author :
Kawasumi, Atsushi ; Takeyama, Yasuhisa ; Hirabayashi, Osamu ; Kushida, Keiichi ; Tachibana, Fumihiko ; Niki, Yusuke ; Sasaki, Shinichi ; Yabe, Tomoaki
Author_Institution :
Center for Semicond. R&D, Toshiba Corp., Kawasaki, Japan
Abstract :
A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.
Keywords :
SRAM chips; amplifiers; signal generators; statistical analysis; access time reduction; bitline delays; delay distribution; size 28 nm; size 40 nm; statistical method; ultralow voltage SRAM; variation tolerant sense amplifier timing generator; worst-case timing-generation scheme; Delay; Generators; Logic gates; Random access memory; Simulation; Statistical analysis; SRAM; random-variation; statistical-method;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243809
