Title :
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS
Author :
Toifl, Thomas ; Ruegg, Michael ; Inti, Rajesh ; Menolfi, Christian ; Brändli, Matthias ; Kossel, Marcel ; Buchmann, Peter ; Francese, Pier Andrea ; Morf, Thomas
Author_Institution :
IBM Res. GmbH, Zurich, Switzerland
Abstract :
This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.
Keywords :
CMOS integrated circuits; decision feedback equalisers; error statistics; silicon-on-insulator; 15-tap SC-DFE RX data path; 15-tap decision feedback equalizer; BER; CTLE; ESD; PRBS31 data; SC-DFE approach; SOI-CMOS technology; bit rate 30 Gbit/s; continuous-time linear equalizer; power 3.1 mW; quarter-rate triple-speculation; receiver data path; size 32 nm; switched-cap-decision feedback equalizer approach; Bandwidth; Bit error rate; CMOS integrated circuits; Clocks; Decision feedback equalizers; Electrostatic discharges; Latches;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243810
