VLSI circuits for decomposing binary integers into signed power-of-two terms

Author

Lim, Yong Ching ; Liu, Bede ; Evans, Joseph B.

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore

fYear

1990

fDate

1-3 May 1990

Firstpage

2304

Abstract

If the coefficients of a digital filter are approximated by the sum of signed power-of-two terms, there will be a significant reduction in the area used and an improvement in the speed of custom implementations at the expense of a slight frequency-response deterioration. The authors present two circuits for extracting from a given integer a prescribed number of signed power-of-two terms whose sum is the closest approximation to that given integer. One of these circuits is bit-serial and the other is bit-parallel. Example layouts in a CMOS process are given

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; digital arithmetic; integrated logic circuits; CMOS process; VLSI circuits; binary integer decomposition; bit-parallel; bit-serial; custom implementations; digital IC; digital filter coefficients; frequency-response deterioration; signed power-of-two terms; Adaptive filters; Arithmetic; CMOS process; CMOS technology; Circuits; Digital filters; Frequency response; Hardware; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112470

Filename

112470