A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS

Author

Takemoto, Takashi ; Yamashita, Hiroki ; Kamimura, Takehito ; Yuki, Fumio ; Masuda, Noboru ; Toyoda, Hidehiro ; Chujo, Norio ; Kogo, Kenji ; Lee, Yong ; Tsuji, Shinji ; Nishimura, Shinji

Author_Institution

Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan

fYear

2012

fDate

13-15 June 2012

Firstpage

106

Lastpage

107

Abstract

A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.

Keywords

CMOS integrated circuits; noise; optical links; optical transceivers; CMOS; analog FE tolerant; analog front end; electrical signal; noise canceller; one-chip transceiver; optical backplane; optical link; optical signal; optical transceiver; power 2.2 W; power consumption; power supply variation; redundant data format conversion; size 65 nm; High speed optical techniques; Integrated optics; Iron; Noise cancellation; Optical feedback; Power supplies; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243812

Filename

6243812