DocumentCode :
2661556
Title :
Realization of extensions to Faddeev algorithm on array of SIMD processors
Author :
Dinh Le, H.V. ; Perkowski, Marek A.
Author_Institution :
Dept. of Electr. Eng., Portland State Univ., OR, USA
fYear :
1990
fDate :
1-3 May 1990
Firstpage :
2312
Abstract :
Vertical, horizontal, and two-dimensional extensions are presented for the new Faddeev-algorithm-based systolic architecture for matrix computations presented by H.V.D. Le and M.A. Perkowski (Proc. Int. Con. on Computing and Informati ICCI ´89, Ontario, Canada, 1989). It has essential advantages over previous architectures of this type and finds various applications. Extensions to the Faddeev algorithm can be used in many problems, including the Karmarkar algorithm. The extensions described not only increase system throughput by two to fourfold but also enhance the inherent programmability of Faddeev´s algorithm. This allows the architecture to perform very complex matrix calculations
Keywords :
digital arithmetic; mathematics computing; matrix algebra; parallel algorithms; systolic arrays; Faddeev algorithm; Karmarkar algorithm; SIMD processors; horizontal extension; matrix computations; programmability; systolic architecture; two-dimensional extensions; vertical extension; Application software; Circuit synthesis; Computer architecture; Computer vision; Robot vision systems; Signal design; Signal processing; Signal processing algorithms; Systolic arrays; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
Type :
conf
DOI :
10.1109/ISCAS.1990.112472
Filename :
112472
Link To Document :
بازگشت