Architectural design styles in the VLSI implementation of real discrete Fourier transform

The real discrete Fourier transform (RDFT) is an orthogonal transform with sampled frequency responses which corresponds to the Fourier series of real valued sampled signals. Fast algorithms for computing the real discrete Fourier transform (FRFT) use Given´s planar rotation as the basic computing kernel instead of the complex butterfly used in the FFT computation. Two approaches for the VLSI implementation of FRFT are presented. The first approach is based on an elegant implementation using a CORDIC (coordinate rotation digital computer) processor. The second approach is based on the implementation using a distributed arithmetic scheme, which reorders the rotation as a sum of products and has the advantage of efficient mechanization. The global communication inherent in the FRFT algorithm is circumvented using the systolic elevator concept, which assures local communication in the algorithm. The proposed architectures exploit regularity and are quite simple and modular, hence very attractive for VLSI implementation