Title :
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM
Author :
Park, Youn Sung ; Blaauw, David ; Sylvester, Dennis ; Zhang, Zhengya
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
Memory dominates the power consumption of high-throughput LDPC decoders. A 700 MHz refresh-free embedded DRAM (eDRAM) is designed as a low-power memory to retain data for the required access window. 321-kb eDRAM arrays are integrated in a 1.6 mm2, 65nm LDPC decoder suitable for IEEE 802.11ad. The LDPC decoder consumes 38 mW for a 1.5 Gb/s throughput at 90 MHz and 10 decoding iterations, and it achieves up to 9 Gb/s at 540 MHz.
Keywords :
DRAM chips; decoding; low-power electronics; parity check codes; IEEE 802.11ad; bit rate 1.5 Gbit/s; eDRAM arrays; frequency 540 MHz; frequency 700 MHz; frequency 90 MHz; high-throughput LDPC decoders; low-power memory; power 38 mW; power consumption; refresh-free embedded DRAM; storage capacity 321 Kbit; Decoding; Iterative decoding; Random access memory; Signal to noise ratio; Throughput; Voltage measurement;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243816
