DocumentCode :
2661606
Title :
Benchmark results for high-speed 4-bit accumulators implemented in indium phosphide DHBT technology
Author :
Turner, Steven Eugene ; Kotecki, David E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Maine Univ., Orono, ME, USA
fYear :
2004
fDate :
4-6 Aug. 2004
Firstpage :
22
Lastpage :
27
Abstract :
High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double heterojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.
Keywords :
III-V semiconductors; direct digital synthesis; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; millimetre wave bipolar transistors; 4 bits; 40 GHz; InP; double heterojunction bipolar transistor; high-speed accumulators; power consumption; supply voltage; Benchmark testing; Circuit testing; Clocks; DH-HEMTs; Energy consumption; Frequency; Heterojunctions; Indium phosphide; Large-scale systems; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Devices, 2004. Proceedings. IEEE Lester Eastman Conference on
Print_ISBN :
981-256-196-X
Type :
conf
DOI :
10.1109/LECHPD.2004.1549666
Filename :
1549666
Link To Document :
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