An efficient heuristic approach to state encoding for PLA-based sequential circuits

An efficient heuristic approach to state encoding of sequential circuits is described. With the approach, the total area of silicon used by the PLA-based two-level implementation for combinational circuits can be minimized. Apart from the conventional methods, in which state encoding is determined one after another in a predetermined order of states, this approach is distinctive in that top priority is given to how to seek cubes which constitute a cover to be allocated to each group of states (where a group of states denotes a set of states which have the same next state and the same output for an input) on the basis of a magnitude estimation of cubes so that the total number of cubes to be used can be minimized. Implementation results are also shown to reveal how this approach is of practical use