A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS

Author

Hsu, Steven ; Agarwal, Amit ; Anders, Mark ; Kaul, Himanshu ; Mathew, Sanu ; Sheikh, Farhana ; Krishnamurthy, Ram ; Borkar, Shekhar

Author_Institution

Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA

fYear

2012

fDate

13-15 June 2012

Firstpage

118

Lastpage

119

Abstract

A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.

Keywords

CMOS logic circuits; shift registers; 1R-1W cells; 2-way 12b reduced mantissa precision modes; 4-way 6b reduced mantissa precision modes; area-efficient windowing; frequency 2.8 GHz; mode-dependent gating; shuffler; size 32 nm; three-read-two-write multiprecision floating-point register file; ultralow-voltage read-write circuits; voltage 1.05 V; voltage 400 mV; CMOS integrated circuits; Decoding; Energy efficiency; Logic gates; Multiplexing; Registers; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243818

Filename

6243818