Title :
Room-temperature bias acceleration test for data retention screening on SONOS nonvolatile memory devices
Author :
Hwang, Jeong-Mo ; Wallinger, Todd ; Hackbarth, Holden
Author_Institution :
Simtek Corp, Colorado Springs
Abstract :
We demonstrated a significant charge loss by a small DC bias applied to the SONOS gate. This charge loss can be correlated with that of a high-temperature bake. A bias acceleration test can be useful for wafer-level retention screening. The results also suggest that the gate bias for data readshould be set around 0V to minimize the gate read disturbance. More work is underway to investigate the mechanism of charge loss, the recall disturbance in nvSRAM, etc.
Keywords :
integrated circuit testing; integrated memory circuits; life testing; logic gates; logic testing; nitrogen compounds; random-access storage; silicon compounds; transistors; wafer-scale integration; SONOS nonvolatile memory devices; charge loss; high-temperature bake; logic gates; room-temperature bias acceleration test; wafer-level data retention screening; Acceleration; Charge carrier processes; Data engineering; Educational institutions; Life estimation; Nonvolatile memory; Reliability engineering; SONOS devices; Temperature; Testing;
Conference_Titel :
Semiconductor Device Research Symposium, 2007 International
Conference_Location :
College Park, MD
Print_ISBN :
978-1-4244-1892-3
Electronic_ISBN :
978-1-4244-1892-3
DOI :
10.1109/ISDRS.2007.4422539
