DocumentCode
2661652
Title
Maximum intrinsic gain degradation in technology scaling
Author
Pude, Mark ; Macchietto, Chris ; Singh, Prashant ; Burleson, Jeff ; Mukund, P.R.
Author_Institution
Rochester Inst. of Technol., Rochester
fYear
2007
fDate
12-14 Dec. 2007
Firstpage
1
Lastpage
2
Abstract
Aggressive device scaling has begun to pose significant problems to the analog design community. For the most part, digital circuitry benefits from the effects of scaling in terms of both faster speeds and decreased power consumption with the exception gate leakage becoming significant. A recent push towards system on a chip (SOC) designs in which both digital and analog components of a system co-exist on the same monolithic substrate has forced many analog designs into these scaled technologies. The effects of scaling have not been as beneficial to the analog component as it has to their digital counterparts.
Keywords
analogue integrated circuits; logic design; system-on-chip; analog design; device scaling; digital circuitry; intrinsic gain degradation; system-on-chip; CMOS technology; Circuit testing; Degradation; Design methodology; Educational institutions; Energy consumption; Large scale integration; Marine technology; Threshold voltage; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium, 2007 International
Conference_Location
College Park, MD
Print_ISBN
978-1-4244-1892-3
Electronic_ISBN
978-1-4244-1892-3
Type
conf
DOI
10.1109/ISDRS.2007.4422541
Filename
4422541
Link To Document