Title :
PLA folding by partitioning
Author :
Lakhani, Gopal ; Kannappan, Karthik
Author_Institution :
Dept. of Comput. Sci., Texas Tech. Univ., Lubbock, TX, USA
Abstract :
A graph-partitioning-based PLA (programmable logic array) folding algorithm is described. It is solved as a row/column reordering problem by following the approach of F.H. Wang et al. (1987). The implementation considers the area of the folded PLA as the cost function. Many experimental results show that the tool produces results superior to those produced by the PLEASURE program. The results are also about as good as those produced by a simulated-annealing-based algorithm
Keywords :
graph theory; logic CAD; logic arrays; CAD; PLA area; PLA folding; computer aided design; cost function; folding algorithm; graph-partitioning-based PLA; programmable logic array; row/column reordering problem; Computer science; Constraint optimization; Cost function; Large scale integration; Partitioning algorithms; Programmable logic arrays; Simulated annealing; Stochastic processes;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112479
