DocumentCode
2661721
Title
High-speed architectures for algorithms with quantizer loops
Author
Parhi, Keshab K.
Author_Institution
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
2357
Abstract
High-speed microelectronic implementation of adaptive equalizers, encoders, and other associated signal processing algorithms is difficult, since the recursive portion of these algorithms contains nonlinear quantization operations. Examples of such algorithms include differential pulse code modulation (DPCM), adaptive DPCM (ADPCM), and differential feedback equalizers (DFEs). In the past, look-ahead computation techniques were successfully applied to create necessary concurrency in linear recursive and some nonlinear recursive operations (such as the add-compare-select operation). Novel computation approaches are presented, and the look-ahead technique is extended to pipeline the feedback loops containing finite-level quantizers. Approaches to pipeline piecewise linear recursive systems are also presented
Keywords
computerised signal processing; digital signal processing chips; equalisers; feedback; pipeline processing; pulse-code modulation; ADPCM; DPCM; adaptive DPCM; differential feedback equalizers; differential pulse code modulation; feedback loops; finite-level quantizers; high-speed architectures; look-ahead computation techniques; microelectronic implementation; nonlinear quantization operations; piecewise linear recursive systems; pipeline; quantizer loops; signal processing algorithms; Adaptive equalizers; Concurrent computing; Feedback loop; Microelectronics; Modulation coding; Piecewise linear techniques; Pipelines; Pulse modulation; Quantization; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112483
Filename
112483
Link To Document