A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

Author

Shin, Seung-Hwan ; Shim, Dong-Kyo ; Jeong, Jae-Yong ; Kwon, Oh-Suk ; Yoon, Sang-Yong ; Choi, Myung-Hoon ; Kim, Tae-Young ; Park, Hyun-Wook ; Yoon, Hyun-Jun ; Song, Young-Sun ; Choi, Yoon-Hee ; Shim, Sang-Won ; Ahn, Yang-Lo ; Park, Ki-Tae ; Han, Jin-Man ;

Author_Institution

Flash Design Team, Samsung Electron., Hwasung, South Korea

fYear

2012

fDate

13-15 June 2012

Firstpage

132

Lastpage

133

Abstract

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

Keywords

NAND circuits; error statistics; flash memories; BER; SLC-to-TLC migration; TLC NAND flash product; bit rate 400 Mbit/s; bit rate 8 Mbit/s; high performance TLC NAND flash memory; programming algorithm; size 20 nm; size 21 nm; storage capacity 64 Gbit; triple-level-cell; word length 3 bit; Algorithm design and analysis; Computer architecture; Couplings; Flash memory; Interference; Performance evaluation; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243825

Filename

6243825