Title :
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS
Author :
Oh, Taehyoun ; Harjani, Ramesh
Author_Institution :
Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane.
Keywords :
CMOS analogue integrated circuits; IIR filters; crosstalk; interference suppression; printed circuits; receivers; BER; CMOS process; XTCR algorithm; XTCR design; analog-IIR networks; bit rate 12 Gbit/s; closely-spaced single-ended PCB traces; crosstalk cancellation-signal reutilization algorithm; lane analog-IIR crosstalk cancellation; signal integrity; signal reutilization receiver; single-ended I/O; size 65 nm; Adders; Bit error rate; Crosstalk; Gain; Optical signal processing; Prototypes; Receivers;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243829
