Title :
Indentification of viable paths using binary decision diagrams
Author :
Ju, Yun-Cheng ; Saleh, Resve A.
Author_Institution :
Coordinated Sci. Lab. Illinois Univ., Urbana, IL, USA
Abstract :
An efficient algorithm for the indentification of viable paths in a combinational logic circuit using binary decision diagrams is described. The viable paths are justified by generating and resolving logic and delay constraints along the critical path based on the stable times and stable values of the side inputs. Results of the analysis, using the ISCAS combinational benchmark circuits, indicate that most of the circuits can be analyzed in a few CPU-seconds
Keywords :
circuit analysis computing; combinatorial circuits; delays; ISCAS combinational benchmark circuits; binary decision diagrams; combinational logic circuit; critical path; delay constraints; logic constraints; side inputs; stable values; viable paths; Boolean functions; Circuit analysis; Circuit analysis computing; Computer networks; Data analysis; Data structures; Delay estimation; Logic; TV; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139991
