Title :
Optimal clocking of circular pipelines
Author :
Sakallah, Karem A. ; Mudge, Trevor N. ; Burks, Timothy M. ; Davidson, Edward S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described
Keywords :
clocks; delays; logic CAD; pipeline processing; circuit delays; circular pipelines; clock skews; minimum cycle time; multi-phase clocks; single phase clocks; timing model; Circuit simulation; Circuit synthesis; Clocks; Computer architecture; Delay effects; Flip-flops; Latches; Pipeline processing; Synchronization; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139992
