• DocumentCode
    2662058
  • Title

    A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression

  • Author

    Liu, Tsung-Te ; Rabaey, Jan M.

  • Author_Institution
    Berkeley Wireless Res. Center, Univ. of California, Berkeley, CA, USA
  • fYear
    2012
  • fDate
    13-15 June 2012
  • Firstpage
    158
  • Lastpage
    159
  • Abstract
    A neural signal processor exploits an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to the process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the self-timed processor demonstrates robust sub-threshold operation down to 0.25V, while consuming only 460nW in 0.03mm2 in a 65nm CMOS technology, representing a 4.4X reduction in power compared to the state-of-the-art designs.
  • Keywords
    CMOS logic circuits; asynchronous circuits; biomedical electronics; digital signal processing chips; neural chips; CMOS technology; asynchronous neural signal processor; asynchronous timing strategy; digital processors; inherent leakage suppression; logic topology; power 460 mW; self-timed processor; size 65 nm; voltage 0.25 V; CMOS integrated circuits; Feature extraction; Logic gates; Protocols; Robustness; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4673-0848-9
  • Electronic_ISBN
    978-1-4673-0845-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243838
  • Filename
    6243838