DocumentCode :
2662082
Title :
A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout
Author :
Koide, Tetsushi ; Wakabayashi, Shin´ichi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
fYear :
1998
fDate :
10-13 Feb 1998
Firstpage :
577
Lastpage :
583
Abstract :
This paper presents a timing-driven global routing algorithm based on coarse pin assignment, block reshaping, and positioning for VLSI building block layout. As opposed to conventional approaches, we combine pin assignment and global routing problems into one problem. The proposed algorithm determines global routes, coarse pin assignments, and block shape and positions so as to minimize the chip area and total wire length of nets under the given timing constraints. It is based on an iterative improvement paradigm and performs rip-up and rerouting, block reshaping, and positioning in the manner of simulated evolution taking shapes of soft blocks and routing congestion into consideration until the solution is not improved. The Elmore delay model is adopted for the interconnection delay model. Experimental results show the effectiveness of the proposed algorithm
Keywords :
VLSI; circuit layout CAD; network routing; Elmore delay model; VLSI building block layout; block reshaping; block shape; chip area; coarse pin assignment; global routing; iterative improvement paradigm; timing-driven; total wire length; Delay; Integrated circuit interconnections; Iterative algorithms; Pins; Postal services; Routing; Shape; Timing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
Type :
conf
DOI :
10.1109/ASPDAC.1998.669560
Filename :
669560
Link To Document :
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