• DocumentCode
    2662155
  • Title

    A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB

  • Author

    Taylor, Gerry ; Galton, Ian

  • Author_Institution
    Analog Devices, San Diego, CA, USA
  • fYear
    2012
  • fDate
    13-15 June 2012
  • Firstpage
    166
  • Lastpage
    167
  • Abstract
    A 0.075 mm2 65 nm CMOS VCO-based ΔΣ modulator ADC that operates from a single 0.9-1.2 V supply is presented. Its sample-rate, fs, is tunable from 1.3-2.4 GHz over which the SNDR spans 70-75 dB, the bandwidth spans 5-37.5 MHz, and the minimum SNDR + 10 log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.
  • Keywords
    CMOS integrated circuits; delta-sigma modulation; voltage-controlled oscillators; CMOS VCO-based ΔΣ modulator ADC; FOM; frequency 1.3 GHz to 37.5 GHz; noise figure 70 dB to 160 dB; power dissipation; reconfigurable mostly-digital ΔΣ ADC; voltage 0.9 V to 1.2 V; Calibration; Delay; Frequency modulation; Integrated circuits; Quantization; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4673-0848-9
  • Electronic_ISBN
    978-1-4673-0845-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243842
  • Filename
    6243842
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2662155