• DocumentCode
    2662176
  • Title

    A 71dB dynamic range third-order ΔΣ TDC using charge-pump

  • Author

    Gande, Manideep ; Maghari, Nima ; Oh, Taehwan ; Moon, Un-Ku

  • Author_Institution
    Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
  • fYear
    2012
  • fDate
    13-15 June 2012
  • Firstpage
    168
  • Lastpage
    169
  • Abstract
    A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.
  • Keywords
    CMOS integrated circuits; delta-sigma modulation; time-digital conversion; CMOS process; charge pump; frequency 2.81 MHz; high resolution time-to-digital converter architecture; noise figure 67 dB to 71 dB; noise-shaping quantization; power 2.58 mW; size 0.13 mum; third-order ΔΣ TDC; Capacitors; Charge pumps; Delay; Discharges (electric); Noise shaping; Quantization; Tin;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4673-0848-9
  • Electronic_ISBN
    978-1-4673-0845-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243843
  • Filename
    6243843
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2662176