Title :
A shorted global clock design for multi-GHz 3D stacked chips
Author :
Pang, Liang-Teck ; Restle, Phillip J. ; Wordeman, Matthew R. ; Silberman, Joel A. ; Franch, Robert L. ; Maier, Gary W.
Author_Institution :
Thomas J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
Abstract :
A global clock distribution technique for 3D stacked chips where the clock tree and grid are shorted between strata is presented and compared with a DLL-based technique. Both permit at-speed testing of the strata before and after stack assembly. The shorting-based technique is implemented in a 2-strata eDRAM test chip using an IBM 45nm SOI 3D technology. Operation above 2.5GHz is measured.
Keywords :
DRAM chips; clocks; delay lock loops; silicon-on-insulator; three-dimensional integrated circuits; 2-strata eDRAM test chip; 3D stacked chip; DLL-based technique; IBM 45nm SOI 3D technology; clock tree; delay-locked loop circuit; global clock design; global clock distribution technique; permit at-speed testing; size 45 nm; Clocks; Delay; Electrostatic discharges; Integrated circuit interconnections; Inverters; Testing; Through-silicon vias; 3D chip; GHz; VLSI; clock distribution;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243844
