An architecture of the RISC processor for programmable controllers

In this paper, an instruction set and an architecture of a RISC processor for programmable controllers are proposed. Characteristics of ladder instructions are analyzed by investigation of various existing programs. The instruction set is defined so that existing ladder programs can be reused with simple translation. Bit instructions are designed to directly control the execution of the following word instruction, and thus the processor runs fast with word instructions as well as bit instructions. Translator and simulator are developed to compare the performance with other processors and PCs. Simulations show that the PC with the suggested processor is two times faster than the PC with the general-purpose microprocessor on the same condition