DocumentCode
2662205
Title
A 3-stage Pseudo Single-phase Flip-flop family
Author
Partovi, Hamid ; Yeung, Alfred ; Ravezzi, Luca ; Horowitz, Mark
Author_Institution
Veloce Technol., Inc., Santa Clara, CA, USA
fYear
2012
fDate
13-15 June 2012
Firstpage
172
Lastpage
173
Abstract
This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and 24% lower than the pulsed-latch and the master-slave flip-flop respectively. Measurement results confirm an improvement of at least 300MHz in operating frequency when using the PSPFF in place of the master-slave flip-flop.
Keywords
CMOS integrated circuits; flip-flops; microprocessor chips; nanoelectronics; 3-stage pseudo single-phase flip-flop family; CMOS technology; energy-delay product; fast pulsed-latch; frequency 3 GHz; master-slave flip-flop; microprocessor; size 40 nm; switching energy; voltage 0.9 V; CMOS integrated circuits; Clocks; Flip-flops; Frequency measurement; Latches; Master-slave; Microprocessors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4673-0848-9
Electronic_ISBN
978-1-4673-0845-8
Type
conf
DOI
10.1109/VLSIC.2012.6243845
Filename
6243845
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