Title :
An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS
Author :
Ferriss, Mark ; Plouchart, Jean-Olivier ; Natarajan, Arun ; Rylyakov, Alexander ; Parker, Benjamin ; Babakhani, Aydin ; Yaldiz, Soner ; Sadhu, Bodhisatwa ; Valdes-Garcia, Alberto ; Tierno, José ; Friedman, Daniel
Author_Institution :
T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
Abstract :
A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO´s small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4dB to 1dB, when measured at 70 sites on a 300mm wafer. The PLL has a measured phase noise @10MHz offset of -126.5dBc/Hz at 20.1GHz.
Keywords :
CMOS integrated circuits; calibration; nanoelectronics; phase locked loops; phase noise; silicon-on-insulator; voltage-controlled oscillators; SOI CMOS; VCO small signal gain variation; bandwidth self-calibration scheme; dual-loop PLL; dual-loop architecture; frequency 10 MHz; frequency 20.1 GHz to 26.7 GHz; integral path measurement; integral path self-calibration scheme; loop transfer function; low noise PLL; noise figure 2.4 dB to 1 dB; phase noise; size 300 mm; size 32 nm; Jitter; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Transfer functions; Varactors;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243847
