Title :
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance
Author :
Lee, Yu-Huei ; Peng, Shen-Yu ; Wu, Alex Chun-Hsien ; Chiu, Chao-Chang ; Yang, Yao-Yi ; Huang, Ming-Hsin ; Chen, Ke-Horng ; Lin, Ying-Hsi ; Wang, Shih-Wei ; Yeh, Ching-Yuan ; Huang, Chen-Chih ; Lee, Chao-Cheng
Author_Institution :
Inst. of Electr. Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm2 in 40nm CMOS.
Keywords :
CMOS logic circuits; asynchronous circuits; phase locked loops; voltage control; CMOS; MIPS performance; PLL-modulated fast-DVS power management; bidirectional asynchronous wave pipeline; current 50 nA; hybrid power management operation; low-dropout regulator; phase amplifier; quiescent current asynchronous digital-LDO; size 40 nm; switching regulator; CMOS integrated circuits; Digital signal processing; Hybrid power systems; Pipelines; Power demand; Regulators; Voltage control;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243848
