Effects of buffer layer thickness and doping concentration on SiC MESFET characteristics

Two-dimensional simulations have been carried out using the Atlas® device simulator to investigate the effects of the buffer layer thickness and doping concentration on the electrical characteristics of the SiC MESFET. The variations of transconductance, output resistance, gate-source capacitance, gate-drain capacitance and (cutoff frequency) f_T with respect to the change in buffer layer thickness and doping concentration have been investigated. It is observed that the performances of MESFET can be improved by reducing the leakage of channel carrier into the substrate at high drain bias, which is achieved by increasing buffer layer doping density and/or increasing buffer layer thickness. For a SiC MESFET with buffer layer thickness of 0.3μm and gate length of 1μm, drain current increases from 0.1 A/μm to above 0.45A/μm as the buffer layer doping density is decreased from 1.9×10¹⁷ cm^-3 to 1×10¹⁶ cm^-3. The simulations were carried out at a gate-source voltage of -1V and a drain-source voltage of 15V. Under similar conditions, the output resistance decreases from 1.2×10⁶ Ω/μm to 1.0×10⁵ Ω/μm, and the transconductance decreases from 5.9mS/μm to 5.3mS/μm, and f_T decreases from 11GHz to 8GHz.