DocumentCode
2662305
Title
An architecture for asynchronous FPGAs
Author
Wong, Catherine G. ; Martin, Alain J. ; Thomas, Peter
Author_Institution
Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
fYear
2003
fDate
15-17 Dec. 2003
Firstpage
170
Lastpage
177
Abstract
We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage, and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.
Keywords
asynchronous circuits; delay circuits; field programmable gate arrays; logic arrays; asynchronous FPGA; asynchronous field programmable gate array; asynchronous pipeline stage; logic cell; place-and-route; quasi delay insensitive interconnects; timing issues; CMOS logic circuits; Clocks; Delay; Field programmable gate arrays; Logic design; Logic devices; Pipelines; Programmable logic arrays; Programmable logic devices; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN
0-7803-8320-6
Type
conf
DOI
10.1109/FPT.2003.1275745
Filename
1275745
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