Title :
A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity
Author :
Elshazly, Amr ; Inti, Rajesh ; Talegaonkar, Mrunmay ; Hanumolu, Pavan Kumar
Author_Institution :
Oregon State Univ., Corvallis, OR, USA
Abstract :
A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10pspp jitter degradation with 200mVpp noise).
Keywords :
CMOS digital integrated circuits; delay lock loops; digital phase locked loops; integrated circuit noise; jitter; low-power electronics; sensitivity; CMOS process; TDC; frequency 1.5 GHz; high digital PLL; in-band noise digital phase-locked loop; low power regulator; output jitter reduction; power 1.35 mW; ring-oscillator based DPLL; size 0.13 mum; supply-noise sensitivity; time 10 ps; voltage 200 mV; worst-case noise sensitivity; Jitter; Phase locked loops; Phase noise; Regulators; Sensitivity;
Conference_Titel :
VLSI Circuits (VLSIC), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0848-9
Electronic_ISBN :
978-1-4673-0845-8
DOI :
10.1109/VLSIC.2012.6243853
