A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW

Author

Zhang, Xin ; Chen, Po-Hung ; Ryu, Yoshikatsu ; Ishida, Koichi ; Okuma, Yasuyuki ; Watanabe, Kazunori ; Sakurai, Takayasu ; Takamiya, Makoto

Author_Institution

Univ. of Tokyo, Tokyo, Japan

fYear

2012

fDate

13-15 June 2012

Firstpage

194

Lastpage

195

Abstract

A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.

Keywords

CMOS integrated circuits; PWM power convertors; adaptive control; delay lines; digital control; low-power electronics; voltage control; CMOS; LSV scheme; OGB; adaptive power supply voltage control; clock gated digital PWM controller; die-to-die delay variations; input on-chip gate boosted buck converter; linear delay trimming; logarithmic stress voltage scheme; power 2 muW to 50 muW; size 40 nm; voltage 0.4 V; voltage 0.45 V; Clocks; Delay; Delay lines; Logic gates; Pulse width modulation; Stress; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243856

Filename

6243856