FPGA based EBCOT architecture for JPEG 2000

Author

Gangadhar, Manjunath ; Bhatia, Dinesh

Author_Institution

Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA

fYear

2003

fDate

15-17 Dec. 2003

Firstpage

228

Lastpage

233

Abstract

In this paper a high speed FPGA based implementation of Embedded Block Coding with Optimized Truncation (EBCOT) algorithm used in JPEG 2000 has been proposed and implemented. The context formation engine used in EBCOT is analyzed and an architecture based on parallel processing of the three coding passes is proposed. The architecture is coded in VHDL and the design is targeted to Xilinx Virtex II FPGA family. When implemented on a XC2V1000 device, the design performs at 56 MHz after place and route. Simulation results show that the design can process a 512×512 image in less than 0.03 seconds and the processing time is reduced by more than 75% compared to sample based implementation and by more than 34% compared to the best architecture known.

Keywords

field programmable gate arrays; hardware description languages; image coding; parallel architectures; 56 MHz; EBCOT algorithm; FPGA based EBCOT architecture; JPEG 2000; VHDL; XC2V1000 device; Xilinx Virtex II FPGA; coding passes; context formation engine; embedded block coding with optimized truncation algorithm; field programmable gate arrays; hardware description languages; joint photographic experts group; parallel processing; processing time; Block codes; Discrete wavelet transforms; Entropy; Field programmable gate arrays; Image coding; Image resolution; Propagation losses; Quantization; Tiles; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on

Print_ISBN

0-7803-8320-6

Type

conf

DOI

10.1109/FPT.2003.1275752

Filename

1275752