An FPGA based coprocessor for large matrix product implementation

Author

Bensaali, F. ; Amira, A. ; Bouridane, A.

Author_Institution

Queen´´s Univ., Belfast, UK

fYear

2003

fDate

15-17 Dec. 2003

Firstpage

292

Lastpage

295

Abstract

Matrix multiplication is very important in many types of applications including image and signal processing. This paper presents an investigation into the design and implementation of matrix product algorithm using different design approaches such as Handel-C and VHDL, where the performance of both programming languages have been presented. Solutions for processing large matrix products based partitioning methodology have been described. The proposed system has been implemented and verified using the RC1000-PP Celoxica board based development platform.

Keywords

coprocessors; field programmable gate arrays; hardware description languages; matrix multiplication; programming languages; FPGA; Handel-C; RC1000-PP Celoxica board; VHDL; coprocessor; image processing; matrix multiplication; matrix product algorithm; partitioning; programming languages; signal processing; Algorithm design and analysis; Computer languages; Coprocessors; Digital control; Field programmable gate arrays; Graph theory; Hardware; Mathematical model; Partitioning algorithms; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on

Print_ISBN

0-7803-8320-6

Type

conf

DOI

10.1109/FPT.2003.1275760

Filename

1275760