Title :
Synchronous logic synthesis: circuit specifications and optimization algorithms
Author :
Damiani, Maurizio ; Micheli, Giovanni De
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Synchronous logic networks are characterized in terms of graphs, logic functions, and synchronous don´t care conditions induced by the external and internal interconnection of the network. Algorithms to compute the don´t care set for each local logic network. Algorithms to compute the don´t care set for each logic function of the network from the synchronous don´t care conditions that characterize the entire network are presented. Such local don´t care conditions can be used to optimize locally each logic function to produce a smaller, faster, and better testable network
Keywords :
logic design; minimisation of switching nets; optimisation; circuit specifications; graphs; local don´t care conditions; local logic functions optimisation; logic functions; optimization algorithms; synchronous don´t care conditions; synchronous logic synthesis; testable network; Circuit synthesis; Combinational circuits; Design optimization; Integrated circuit interconnections; Logic circuits; Logic functions; Logic gates; Logic testing; Network synthesis; Registers;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112533
