ASIC design with OASIS

Author

Kedem, Gershon ; Brglez, Franc ; Kozminski, K.

Author_Institution

Dept. of Comput. Sci., Duke Univ., Durham, NC, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

2580

Abstract

An overview of a cell-based silicon compiler system, called OASIS, that supports rapid implementation of digital application-specific ICs (ASICs) by taking a high-level language description and producing a layout of a testable IC is presented. The major components of the system are the language compiler combined with a logic synthesis system, a mixed-mode multilevel timing simulation and verification system, a test pattern generation system, and an IC layout system. The OASIS system successfully integrates existing public domain tools while adding major new components. Several application-specific ICs that were designed with OASIS are described. A dramatic increase in designer productivity is reported

Keywords

application specific integrated circuits; cellular arrays; circuit layout CAD; digital integrated circuits; ASIC design; IC layout system; OASIS; adding major new components; cell-based silicon compiler system; digital application-specific ICs; high-level language description; increase in designer productivity; integrates existing public domain tools; language compiler; logic synthesis system; mixed-mode ICs; mixed-mode multilevel timing simulation; rapid implementation; test pattern generation system; testable IC; verification system; Application specific integrated circuits; Digital integrated circuits; High level languages; Integrated circuit layout; Integrated circuit testing; Logic testing; Silicon compiler; System testing; Test pattern generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112536

Filename

112536