A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism

In our research, we propose a PARS architecture as a reconfigurable architecture for general purpose. Reconfigurable architectures including the PARS architecture have a serious issue as its configuration data size becomes huge. In case of coarse-grained reconfigurable architectures, the issue is less serious compared with the fine-grained reconfigurable architectures. However, if the unused region on reconfigurable hardware is large, its configuration data includes much invalid information. In this paper, to ease the issue, we have designed a reconfigurable processor which enables to compress valid operations in several successive configuration data into one configuration data and execute it. From the chip design of the processor, the mechanism increases the number of transistor to only 0.17%, and it reduces the size of configuration data for a FEAL cipher program to 28% of the original configuration data size.