Title :
Verification of high level synthesis designs through gate level simulation of compiled module implementations
Author :
Fuhrman, T. ; Thomas, D. ; Murgai, R. ; Un, E.
Author_Institution :
General Motors Res. Labs., Warren, MI, USA
Abstract :
The evaluation of a high-level synthesis system is described. The output of the synthesis system is translated automatically to the input of a commercially available silicon compiler, and the output of the silicon compiler is simulated to determine functional and timing correctness of an experimental design. Results show that a correct design is produced
Keywords :
circuit layout CAD; digital simulation; logic CAD; modules; compiled module implementations; functional correctness; gate level simulation; high level synthesis designs; silicon compiler; timing correctness; Computer architecture; Flow graphs; High level synthesis; Libraries; Mesh generation; Optimizing compilers; Read-write memory; Registers; Routing; Silicon compiler;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112537
