Title :
Table of contents
Abstract :
The following topics are dealt with: optimization; asynchronous digital circuits; asynchronous fully digital delay locked loop; DDR SDRAM data; CAD; arithmetic circuits; clock scheduling; fault tolerance; and self synchronous circuits.
Keywords :
CAD; SRAM chips; asynchronous circuits; circuit optimisation; clocks; delay lock loops; fault tolerance; CAD; DDR SDRAM data; arithmetic circuit; asynchronous digital circuit; asynchronous fully digital delay locked loop; clock scheduling; fault tolerance; optimization; self-synchronous circuit;
Conference_Titel :
Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on
Conference_Location :
Lyngby
Print_ISBN :
978-1-4673-1360-5
DOI :
10.1109/ASYNC.2012.10
