Title :
Statistical Analysis and Optimization of Asynchronous Digital Circuits
Author :
Liu, Tsung-Te ; Rabaey, Jan M.
Author_Institution :
Berkeley Wireless Res. Center, Univ. of California, Berkeley, Berkeley, CA, USA
Abstract :
This paper presents a statistical framework to analyze the performance of CMOS digital circuit in the presence of process variations considering a variety of timing methodologies. We first develop an analytical model that accurately predicts the circuit variability across a wide range of supply voltage and logic depth in 65nm CMOS technology. We then present a statistical analysis model to estimate the respective performance overheads of synchronous, asynchronous bundled-data and dual-rail timing schemes under process variations. The proposed analysis framework combining variability and statistical performance models, enables designers to efficiently evaluate energy and delay performances of CMOS digital circuit, and determine the optimal timing strategy, pipeline depth and supply voltage in the presence of variability.
Keywords :
CMOS digital integrated circuits; asynchronous circuits; circuit optimisation; integrated circuit design; statistical analysis; CMOS digital circuit; CMOS digital circuit delay performance; CMOS technology; asynchronous bundled-data; asynchronous digital circuit; circuit variability; dual-rail timing scheme; logic depth; optimal timing strategy; optimization; pipeline depth; statistical analysis; statistical framework; statistical performance model; supply voltage; synchronous bundled-data; CMOS integrated circuits; Delay; Digital circuits; Integrated circuit modeling; Protocols; Semiconductor device modeling; CMOS digital circuit; asynchronous circuit; energy-delay performance; process variation; statistical analysis; timing methodology;
Conference_Titel :
Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on
Conference_Location :
Lyngby
Print_ISBN :
978-1-4673-1360-5
DOI :
10.1109/ASYNC.2012.21
