DocumentCode :
2662704
Title :
On-chip communication architectures for reconfigurable System-on-Chip
Author :
Lee, Andy S. ; Bergmann, Neil W.
Author_Institution :
Sch. of ITEE, Queensland Univ., Brisbane, Qld., Australia
fYear :
2003
fDate :
15-17 Dec. 2003
Firstpage :
332
Lastpage :
335
Abstract :
On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. The paper surveys existing solutions for SoC and analyses the suitability for rSoC application. It also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.
Keywords :
reconfigurable architectures; system buses; system-on-chip; systems analysis; RSOC design; onchip communication architectures; packet switched network; reconfigurable system on chip; serial bus; system on chip designs; Application specific integrated circuits; Communication system control; Control systems; Costs; Design methodology; Fabrication; Field programmable gate arrays; Integrated circuit interconnections; Joining processes; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN :
0-7803-8320-6
Type :
conf
DOI :
10.1109/FPT.2003.1275770
Filename :
1275770
Link To Document :
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