Title :
Delay-time bounds for on-chip and off-chip interconnection networks
Author_Institution :
State Univ. of New York, NY, USA
Abstract :
A lower bound on the delay time is established for interconnection networks with meshes having (in addition to series resistances and shunting capacitances) inductances, floating capacitances, leakage resistances, and a quite general distribution of parameters. The bound is very readily computed once the input-to-output paths are picked out and the DC gain of the network is determined
Keywords :
delays; ladder networks; monolithic integrated circuits; network topology; DC gain; delay time; delay-time bounds; floating capacitances; inductances; input-to-output paths; leakage resistances; meshes; off-chip interconnection networks; series resistances; shunting capacitances; Capacitance; Capacitors; Delay effects; Delay estimation; Inductors; Integrated circuit interconnections; Multiprocessor interconnection networks; Network-on-a-chip; RLC circuits; Resistors;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112549
