DocumentCode
2662927
Title
Automatic precondition verification for high-level design transformations
Author
Sridhar, Anuradha ; Vemuri, Ranga
Author_Institution
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
2654
Abstract
A precondition verification system for high-level (register-transfer-level) design transformations is described. The system can verify spatial preconditions in terms of the data path composition and topology, as well as temporal preconditions in terms of assertions on the control flow paths. The system is implemented in Prolog and incorporates a mixture of techniques including symbolic equivalence and partial evaluation to effectively verify the preconditions in the presence of arbitrarily nested data-dependent decision points (conditional and iterative constructs) in the control graph. An example which shows how the system can be used for precondition verification is presented
Keywords
PROLOG; graph theory; logic CAD; Prolog; arbitrarily nested data-dependent decision points; control flow paths; data path composition; high-level design transformations; partial evaluation; precondition verification system; register-transfer-level; spatial preconditions; symbolic equivalence; temporal preconditions; Control system synthesis; Control systems; Delay; Flow graphs; Hardware; Registers; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112554
Filename
112554
Link To Document