A novel concurrent error detection circuit for Leading Zero Anticipator

Author

Tao, Yao ; Deyuan, Gao

Author_Institution

Dept. of Comput. Sci. & Eng., Northwestern Polytech. Univ., Xi´´an, China

Volume

6

fYear

2010

fDate

16-18 April 2010

Abstract

Leading Zero Anticipator (LZA) is a technique to calculate the number of leading zeros of the result in parallel with the addition. General algorithms can work effectively for a subtraction, and obtain the leading one position from exponents of operands for an addition or a multiply-add-fused (MAF) operation. However, using exponents to get leading zero number can introduce another error of one bit because of a carry into the leading one position. Moreover, when taking denormalized operands into account, the leading one position does not relate with exponents anymore. This paper presents a novel concurrent error detection circuit for an exact LZA which can work effectively for both addition and subtraction. In addition, a simpler pre-encoding method is employed to reduce the hardware complexity of the concurrent error detection circuit. The total area of the proposed LZA is reduced by 7.5% compared with that of a general LZA.

Keywords

error detection; logic circuits; concurrent error detection circuit; exact LZA; hardware complexity; leading zero anticipator; multiply add fused operation; preencoding method; Added delay; Adders; Computer errors; Computer science; Degradation; Error correction; Hardware; Logic circuits; Logic design; Signal generators; addition and subtraction; concurrent error detection; leading zero anticipator; pre-encoding method;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6347-3

Type

conf

DOI

10.1109/ICCET.2010.5486143

Filename

5486143