Implementation of shift-invariant flow graphs on clock-skewed parallel processing system

A parallel processing system, called the clock-skewed parallel processing system, is proposed. This system uses one or more shared buses as the basic interconnection network between processors, and a fixed amount of clock-skew is maintained between the processing elements. The system can not only handle the interprocessor communications very efficiently, but can explicitly incorporate the interprocessor communication delay into the parallel scheduling model. An efficient scheduling strategy for implementing shift-invariant flow graphs on the system is presented